In various systems applications, SRAMs (Static Random Access Memories), which operate faster than DRAMs, have been employed as routers, hubs or cache memories for CPUs (Central Processing Units). However, the development of highly efficient and multifunctional information and communication systems, mandate an increase in memory capacity. The lower cost per bit of DRAM leads to a more cost efficient storage solution than SRAM. By implementing system storage with DRAM, overall bandwidth can be improved for a wide I/O (input/output) data path or a multibank memory. However, compared with SRAMs, DRAMs are remarkably slower in respect to read/write access. Consequently, the use of DRAMs is performance limited.
Japanese Unexamined Patent Publication (Kokai) No. 2001-84767 (patent document 1) discloses a DRAM including a sense amplifier, shown in FIG. 4 in the attached drawings. (FIG. 3 of Kokai) In Kokai, a P-type sense amplifier PSA is shared by bit line pairs BL and /BL, and is connected between sharing lines SA and /SA. The bit lines BL and /BL are separated from the sharing lines SA and /SA by an isolator BLI. An N-type sense amplifier NSA is connected between the bit lines BL and /BL. An equalizing transistor N20 is connected between the bit lines BL and /BL, which is turned on in response to equalizing signal EQN. The bit lines BL and /BL are equalized to a half power voltage VDD/2 by an equalizing transistor N20. The threshold voltages of N-channel MOS transistors N10 and N11 are set low, e.g., about 0.2 V, so that the N-type sense amplifier NSA can detect a potential difference near the half power voltage VDD/2. Further, set transistor N21 is connected between the sources of transistors N10 and N11 and ground terminal GND, in order to prevent transistors N10 and N11 from turning on in response to the half power voltage VDD/2, which would result in the unintentional enabling of the N-type sense amplifier NSA. When set transistor N21 is turned on upon receiving set signal SETN, N-type sense amplifier NSA is activated.
Unfortunately sense amp precharging consumes additional clock cycles because bit lines BL and /BL are precharged to the half power voltage VDD/2. The additional latency associated with detection and amplification presents another operational difficulty, since the start of the operation of the N-type sense amplifier NSA has to be delayed until set transistor N21 is turned on. Additionally, noise is generated due to capacitive coupling between adjacent bit lines BL and /BL when the set transistor N21 is turned on.
Japanese Unexamined Patent Publication No. 2005-50439 discloses a DRAM that includes a sense amplifier, shown in FIG. 5 in the attached drawings. (FIG. 1 in PUPA No. 2005-50439) In this publication, the DRAM is similar to that in Kokai, except for the connection of the N-type sense amplifier NSA. That is, the gates of transistors N10 and N11 are connected to bit lines /BL and BL, while the drains are connected to sharing lines SA and /SA. When the transistor P1 is turned on in response to the equalizing signal EQP, sharing lines SA and /SA are equalized, and precharged to 1.2 V, which is slightly lower than the power voltage VDD (=1.6 V). Conversely, when the transistor N20 is turned on in response to equalizing signal EQN, bit lines BL and /BL are equalized. Since the voltage on sharing lines SA and /SA is clamped by transistors N6 and N7 of an isolator BLI, the bit lines BL and /BL are precharged to 0.4 V, which is lower by a value equivalent to the threshold voltage (0.8 V) of transistors N6 and N7 than 1.2 V for sharing lines SA and /SA.
According to the DRAM disclosed in PUPA No. 2005-50439, since the parasitic capacitance of bit lines BL and /BL is reduced by a value equivalent to the drain capacitance of transistors N10 and N11, a potential difference between bit lines /BL and BL through the reading operation is slightly increased. However, amplification of the voltage on sharing lines SA and /SA is completed after the set transistor N21 is turned on in response to the set signal SETN. Therefore, the data read period is shorter than the period required in Kokai; however, since the start of the operation of the N-type sense amplifier NSA waits until set transistor N21 is turned on, the data reading period is extended by a value equivalent to this delay.
J. E. Barth, Jr., et al., “Embedded DRAM design and architecture for the IBM 0.11-μm ASIC offering”, IBM J. Res. & Dev., Vol. 46, November 2002, pp. 676-689 (Barth), discloses a DRAM with a sense amplifier, shown in FIG. 6 in the attached drawings (FIG. 8 in Barth) In this document, bit line precharging circuit PC is implemented and bit lines /BL and BL are precharged to ground voltage GND in response to equalizing signal EQN. Further, reference memory cell RMC is connected to bit line /BL, which differs from the bit line BL connected to memory cell MC. When transistor N2 is turned on in response to precharge request signal REQP, half power voltage VDD/2 is applied to reference memory cell RMC. Reference word line RWL is activated together with word line WL, and electric charges are re-distributed into bit line /BL and reference memory cell RMC. Sense amplifiers PSA and NSA employ the voltage of bit line /BL as a reference voltage, and detect and amplify a potential difference between bit lines /BL and BL.
In this case, sense amplifiers PSA and NSA are not shared. Bit lines /BL and BL are connected to local data lines LDL and /LDL through column selection gates N14 and N15, and are also connected to global data lines GDL and /GDL through a local read/write circuit 1.
According to the DRAM disclosed in Barth, since bit lines /BL and BL are precharged to ground GND and the operation of N-type sense amplifier NSA is not accidentally enabled, the sources of transistors N10 and N11 are connected directly to ground terminal GND. On the other hand, since the operation of P-type sense amplifier PSA may be triggered, set transistor P4 is required. Furthermore, since the data lines having a large parasitic capacitance are hierarchically structured, the concomitant increase of parasitic capacitance of bit lines /BL and BL can be suppressed by asserting column selection gates N14 and N15. However, since the local read/write circuit 1 must be additionally provided, the total circuit area required becomes prohibitively large.